**********************
After Init 63 
Before Main Loop 515 
After MAC Entities 16 
ScheduleOutgoingConnections 515 
ScheduleIncomingConnections 110 
AddSubBurstToBurst 15 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 390 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 1281 
MS Receive 63 
After MAC Entities 62 
ScheduleOutgoingConnections 375 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 375 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 15 
BS Transmit 1000 
MS Receive 32 
After MAC Entities 31 
ScheduleOutgoingConnections 390 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 390 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 1015 
MS Receive 32 
After MAC Entities 31 
ScheduleOutgoingConnections 235 
ScheduleIncomingConnections 93 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 297 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 781 
MS Receive 63 
After MAC Entities 15 
ScheduleOutgoingConnections 203 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 203 
ScheduleIncomingConnections 79 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 657 
MS Receive 46 
After MAC Entities 47 
ScheduleOutgoingConnections 266 
ScheduleIncomingConnections 94 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 15 
ScheduleOutgoingConnections 235 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 766 
MS Receive 47 
After MAC Entities 15 
ScheduleOutgoingConnections 219 
ScheduleIncomingConnections 94 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 219 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 688 
MS Receive 47 
After MAC Entities 15 
ScheduleOutgoingConnections 219 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 250 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 719 
MS Receive 31 
After MAC Entities 32 
ScheduleOutgoingConnections 203 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 218 
ScheduleIncomingConnections 94 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 687 
MS Receive 47 
After MAC Entities 16 
ScheduleOutgoingConnections 265 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
ScheduleOutgoingConnections 235 
ScheduleIncomingConnections 78 
AddSubBurstToBurst 0 
AllocateMemoryForDlSlots 0 
BS Transmit 750 
MS Receive 47 
